1. Technical Field
The present disclosure relates to a phase-change memory device having a circuit that discharges leakage currents in deselected bitlines and a method for discharging leakage currents in deselected bitlines of a phase-change memory device.
2. Description of the Related Art
As is known, phase change memories are formed by memory cells connected at the intersections of bitlines and wordlines and comprising each a memory element and a selection element. A memory element comprises a phase change region made of a phase change material, i.e., a material that may be electrically switched between a generally amorphous and a generally crystalline state across the entire spectrum between completely amorphous and completely crystalline states.
Typical materials suitable for the phase change region of the memory elements include various chalcogenide elements. The state of the phase change materials is non-volatile, absent application of excess temperatures, such as those in excess of 150° C., for extended times. When the memory is set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reprogrammed, even if power is removed.
Selection elements may be formed according to different technologies, for example they can be implemented by diodes, by MOS transistors or bipolar transistors.
With reference to FIG. 1, a phase-change memory device 1 comprises an array 2 of PCM cells 3, arranged in rows and columns and connected to a row decoder 6 receiving row address signals ROW_ADDR and to a multiplexer 5 controlled by a column decoder 7 receiving column address signals COL_ADDR. The multiplexer 5 is connected to a write/read unit 8 including all the components (such as sense amplifiers, comparators, charge pumps, reference cells, voltage sources, voltage regulators) necessary for writing or reading the PCM cells 3.
Each PCM cell 3 comprises a phase-change memory element 11 and a selection element 12 coupled in series. Each phase-change memory element 11 includes a portion of a phase-change material and is therefore suitable for storing data in form of respective resistance levels associated to different phases of the phase-change material, as above explained. In the embodiment shown, the selection elements 12 are a PNP bipolar transistors controlled to allow current to flow through the respective memory elements 11 during reading and programming/verifying operations. Each phase-change memory element 11 is directly connected to a respective bit line BL and is connected to a respective word line WL through the selection element 12.
Groups of PCM cells 3 are selectively addressable by the row decoder 6 and the multiplexer 7, as specified by address signals ROW_ADDR and COL_ADDR. The multiplexer 5 and the write/read unit 8 bias selected bitlines BL to biasing voltages, depending on the operating phase, and disconnect unselected bitlines BL, which are thus floating. The row decoder 6 connects selected word lines WL to a low voltage (close to ground) and unselected word lines 16 to a relatively high voltage (typically 1.3 V during reading and 3.8 V during writing).
Each bitline BL is also connected to an own discharge transistor 15. Discharge transistors 15 are NMOS transistors having drain terminals connected to own bitlines BL, gate terminals connected together and receiving a control signal DIS and source terminals connected to ground.
FIG. 1 also shows capacitors 16, representing the capacitance of the bitlines BL and thus connected each between an own bitline BL and ground.
In FIG. 1, three bitlines BLj, BLj+1 and BLm and two wordlines WLi and WL1+1 are shown. The cells 3, the memory elements 11 and the selection elements 12 are thus identified also with a pedal corresponding to the wordline WL and the bitline BL they are coupled to. Analogously, discharge transistors 15 and capacitors 16 are identified with a subscript corresponding to the respective bitline BLj, BLj+1 and BLm, .
The discharge transistors 15 have the aim of discharging leakage currents flowing along the respective bitlines. In particular, during standby or before a reading/writing operation, all the bitlines are left floating and the wordlines are biased at a high voltage VPCX. Furthermore, control signal DIS is high and maintains the discharge transistors 15 on. Thus, all the bitlines BL are connected to ground. In such a situation, the base-emitter junctions of the selection elements 12 are inversely biased and conduct each a discharge current flowing from the row decoder 6 toward ground through the bitlines and the discharge transistors 15. Thereby, the voltage on the bitlines BL cannot increase and the capacitors 16 are discharged.
During a proper reading/writing operation, the discharge transistors 15 are switched off by the control signal DIS; the selected wordline is grounded; the selected bitline is brought to a value VBL, as required by the specific operation; the deselected wordlines are brought to a high value VPCX and the deselected bitlines are left floating.
For example, if cell 3i,j is to be read or written, wordline WLi is grounded and bitline BLj is biased to voltage VBL. Therefore, a current Iop flows through cell 3i,j. The cells 3i+1,j+1, 3i+1,m, connected to the deselected bitlines BLj+1, . . . , BLm and to the deselected wordline WLi+1 conduct a leakage current IL which flows toward the cells 3i,j+i, . . . , 3i,m connected to the selected wordline WLi and the deselected bitlines BLj+1, . . . , BLm. This leakage current IL is a disturbance. In fact, depending of the temperature and on the number of bitlines, it can cause the voltage on the unselected bitlines to increase up to the switch-on value of the deselected selection elements 11i,j+i, . . . , 11i,m connected to the selected wordline WLi, causing an erroneous reading of the deselected memory elements 3i,j+i, . . . , 3i,m.
For example, if the threshold voltage Vth of the selection elements 11 at 120° C. is Vth=0.6 V, a critical condition occurs when the voltage on a generic deselected bitline reaches VBL=0.6+0.6=1.2 V. In the worst condition (when the memory element connected to the selected bitline is in the amorphous state and has a resistance of 1 MΩ), the current flowing through the deselected cells 3i,j+i, . . . , 3i,m is 0.6/106=600 nA.
If 2000 cells are connected to each bitline BL, the cell leakage current IL requested from each non-selected cell 3i+1,j+1, 3i+1,m to cause switch-on of the cells 3i,j+i, . . . , 3i,m is IL=600/2000=300 pA. If the voltage on the deselected wordlines VPCX=4.5 V, the above cell leakage current IL is reached, since the base-to-emitter voltage on each deselected selection elements 11i,j+i, . . . , 11i,m is aboutVBE=−(4.5−1.2)V=−(3.3)V. 
To solve this problem, U.S. Pat. No. 7,092,277 provides a dummy bitline, connected to dummy cells, in turn connected to the wordlines of the memory array. The dummy bitline is connected to the bitlines of the memory array through a current mirror circuit and forces a preset discharge current through the bitlines. Thus, the deselected bitlines cannot be charged at dangerous voltage levels.
However, this solution entails regulation circuitry that increases the power dissipation.